Miniaturization of an LSI has recently progressed due to advancement of transistor technology. Under such a situation, an architecture, such as systolic array or multiprocessor, that uses a large number of calculation units to exhibit a high parallelism attracts lot of attentions. Whether system performance can be improved or not depends upon how it makes possible for the highly parallel processing architecture to enhance efficiency of traffic of data transfer between memories.
In general, a DMA transfer is used for data transfer between memories in the abovementioned system. FIG. 10 is a view showing a configuration of a DMA transfer apparatus which is a background technique of the present invention. A DMA controller 107 for controlling DMA transfer includes a parameter register 101, a DMA control section 100, and IF 106.
Further, an external shared memory 102, an internal memory 103, a calculation core 108, and a CPU 109 are arranged around the DMA controller 107. The DMA controller 107, external shared memory 102, and CPU 109 are connected to data buses 110 and 111.
In the DMA transfer, the CPU 109 does not directly control data transfer from the external shared memory 102 to internal memory 103. That is, as shown in FIG. 10, parameters such as a memory address offset, data number, and the like are set in the DMA controller 107 so as to allow the DMA controller 107 to control the data transfer. By performing the DMA transfer, a load of the CPU 109 can be reduced.
Techniques relating to the DMA transfer are disclosed in, e.g., JP-A-2001-154846 (Patent Document 1), JP-A-2006-155490 (Patent Document 2), JP-A-05-244167 (Patent Document 3), JP-A-05-336380 (Patent Document 4), and JP-A-10-040399 (Patent Document 5).    Patent Document 1: JP-A-2001-154846    Patent Document 2: JP-A-2006-155490    Patent Document 3: JP-A-05-244167    Patent Document 4: JP-A-05-336380    Patent Document 5: JP-A-10-040399